The background description provided here is for the purpose of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent it is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure.
Substrate processing systems may be used to deposit and etch film on a substrate such as a semiconductor wafer. The substrate processing systems typically include a processing chamber, a gas distribution device and a substrate support. During processing, the substrate is arranged on the substrate support. Different gas mixtures may be introduced into the processing chamber and radio frequency (RF) plasma may be used to activate chemical reactions.
As gate pitch decreases, parasitic capacitance between gates of transistors has increasingly become important. Parasitic capacitance adversely impacts power consumption and switching speed. Efforts have been made to reduce a dielectric constant (k) of the gate stack. Spacer film located between gates and a source/drain contact may also impact the effective k value of the gate stack. Current suggestions for reducing the effective k value of the gate stack include lowering the k value of film used for the gates or spacers or forming airgaps in the spacer film.
Forming an airgap in the spacer film has been used due to the low dielectric constant k value of air. Challenges include creating, burying and sealing the airgap sufficiently low in the feature such that the airgap remains sealed and protected during subsequent chemical mechanical polishing (CMP). In addition, a sufficient over-etch margin should be provided. Conventional chemical vapor deposition (CVD) processes may be used to create airgaps. However, the airgaps created by CVD processes are not buried low enough inside features such as trenches and damage may occur during subsequent processing.
Referring now to FIGS. 1-3, an example of a method for creating airgaps in spacers is shown. In FIG. 1, a substrate 50 includes an underlying layer 52 and metal gates 54-1 and 54-2 and source/drain contact 56 that are arranged on the underlying layer 52. Self-aligning contact (SAC)'s 58-1 and 58-2 are arranged on the metal gates 54-1 and 54-2, respectively. Spacers 60-1, 60-2, 60-3 and 60-4 (collectively spacers 60) are arranged between the metal gates 54-1 and 54-2 and the source/drain contact 56. The spacers 60 may be made of silicon nitride (SiN), silicon dioxide (SiO2), or another type of film.
In FIG. 2, selective etching is performed to remove the spacers 60. In FIG. 3, spacers 70-1, 70-2, 70-3 and 70-4 (collectively spacers 70) are deposited and include airgaps 72-1, 72-2, 72-3 and 72-4 (collectively airgaps 72). However, the airgaps 72 are typically located relatively close to an upper surface of the spacers 70. As a result, defects can occur if the airgap is exposed during chemical mechanical polishing (CMP). In addition, an increased over-etch margin is desired.